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W9825G6JH
10.4 Mode Register Set Cycle
t RSC
CLK
CS
RAS
CAS
WE
t CMS
t CMS
t CMS
t CMS
t AS
t CMH
t CMH
t CMH
t CMH
t AH
A0-A12
BS0,1
Register
set data
next
command
A0
A1
Burst Length
A2
0
A0
A1 A0
A0 0
Burst Length
Sequential Interleave
1 1
A2
0
0
1
A0
A0
1
0
2
4
2
4
A3
A4
A5
Addressing Mode
CAS Latency
0
1
1
1
1
1
1
1
A0
A0
A0
A0
A0
1
0
1
0
1
8
Reserved
Full Page
8
Reserved
A6
A3
A0
Addressing Mode
A7
A0
"0"
(Test Mode)
0
1
Sequential
Interleave
A8
"0"
Reserved
A6
A0
A5 A4
CAS Latency
A9
A0
A10
A11
A12
"0"
"0"
"0"
Write A0 Mode
Reserved
0
0
0
0
1
1
1
A0
A0
A0
A0
A0
A0
A9
0
1
0
1
0
Reserved
Reserved
2
3
Reserved
Single Write Mode
BS0
BS1
"0"
"0"
0
1
Burst read and Burst write
Burst read and single write
* "Reserved" should stay "0" during MRS cycle.
Publication Release Date: Mar. 13, 2014
- 21 -
Revision: A09
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